The project partners will conduct joint research by combining ongoing research projects, with the aim to advance the state-of-the-art in the design of reliable digital integrated circuits. Key research goals include: (i) investigate the combined impact of transient and permanent fault effects, from device level up to system level, (ii) investigate new algorithms for time-efficient reliability analysis of complex designs, (iii) investigate techniques for cost-effective reliability optimization of complex digital designs, (iii) establish a cross-layer reliability design flow by integrating available fault models, analysis algorithms and optimization techniques, and (iv) verify reliability analysis and optimization results on complex test circuits and different semiconductor technologies.